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ADP2102
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
Parameter
AVIN, EN, MODE, FB/OUT to AGND
LX to PGND
PVIN to PGND
PGND to AGND
AVIN to PVIN
Operating Ambient Temperature Range
Junction Temperature Range
Storage Temperature Range
Soldering Conditions
Rating
?0.3 V to +6 V
?0.3 V to (V IN + 0.3 V)
?0.3 V to +6 V
?0.3 V to +0.3 V
?0.3 V to +0.3 V
?40°C to +85°C 1
?40°C to +125°C
?65°C to +150°C
JEDEC J-STD-020
Junction-to-ambient thermal resistance (θ JA ) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent on
the application and board layout. In applications where high
maximum power dissipation exists, attention to thermal board
design is required. The value of θ JA may vary, depending on PCB
material, layout, and environmental conditions. Specified value
of θ JA is based on a 4-layer, 4 in × 3 in, 2 1/2 oz copper board,
as per JEDEC standards. For more information, see Application
Note AN-772, A Design and Manufacturing Guide for the Lead
1
The ADP2102 can be damaged when junction temperature limits are exceeded.
Frame Chip Scale Package (LFCSP) .
Monitoring ambient temperature does not guarantee that T J is within the
specified temperature limits. In applications where high power dissipation
and poor thermal resistance are present, the maximum ambient temperature
may have to be derated. In applications with moderate power dissipation
and low PCB thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature is within
Table 3. Thermal Resistance
Package Type
8-Lead LFCSP
Maximum Power Dissipation
θ JA
54
0.74
Unit
°C/W
W
specification limits. The junction temperature (T J ) of the device is dependent
on the ambient temperature (T A ), the power dissipation of the device (PD),
and the junction-to-ambient thermal resistance of the package (θ JA ). Maximum
junction temperature (T J ) is calculated from the ambient temperature (T A )
and power dissipation (PD) using the formula T J = T A + ( θ JA × PD ). Unless
otherwise specified, all other voltages are referenced to AGND.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
BOUNDARY CONDITION
Natural convection, 4-layer board, exposed pad soldered to PCB.
ESD CAUTION
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. B | Page 4 of 24
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